Analog Implementation of Ontogenic Neural Networks for RF Built-In Self-Test

We introduce an analog implementation of an ontogenic neural network (ONN) model and investigate its applicability to the field of built-in self-test (BIST) of RF circuits. Our chip consists of a reconfigurable array of synapses and neurons operating below threshold and featuring sub-μW power consumption. The synapse circuits employ dynamic weight storage for fast bidirectional weight updates during training. The learned weights are copied onto the analog floating gate (FG) memory for permanent storage. Training is performed using a chip-in-the-loop strategy by the cascade-correlation learning algorithm. A benchmark XOR task is employed to evaluate the system performance. Finally, the network is trained to distinguish faulty from functional LNA chips using a set of low-cost sensor measurements.